1. Field of the Invention
The present invention relates to clock signal sources for use in computer and other electronic systems and, in particular, to clock doubler circuits for doubling the frequency of an input clock signal.
2. Description of the Related Art
Systems employing computer processors often provide one or more clock sources which can be used as a system clock to drive the processor, other components of the system, or the entire system. It is sometimes desired to provide a clock signal having a faster frequency than that of a given clock source available in the system. For example, it may be desired to double the clock signal generated by a given clock source.
Clock doubler circuits are often utilized for this purpose. Both the clock doubler and associated system components may be fabricated as an integrated circuit (IC), within a semiconductor chip. Chips are formed in the substrate of a physical wafer, e.g. a silicon wafer. Typically, several chips are formed in each wafer. A wafer is a very thin, flat disc of a given diameter. The manufacturing process consists of operations on the surface and substrate of the wafer to create a number of chips. Once the wafer is completely processed, it is cut up into the individual chips, the size of which depends on the number of components and complexity of each chip.
One conventional type of clock doubler circuit uses a delay element designed to shift the original clock edges by approximately one quarter cycle. This shifted clock signal is then xe2x80x9cmultipliedxe2x80x9d or combined with the original clock signal with a combiner such as an exclusive-or (XOR) gate to produce a clock signal having twice the frequency of the original clock signal.
Unfortunately, the delays introduced by such delay elements vary over process, temperature, power supply voltage, and the like. This causes the duty cycle of the output clock (i.e., ratio of time spend on versus off, which are ideally equal) to vary greatly with process and temperature, which is undesirable. Compensation circuitry may be employed to ensure that the delay is sufficiently close to a quarter of a clock cycle. However, the compensation circuit or mechanism can itself be complex to design, costly in terms of chip area required, or otherwise undesirable, inefficient, or impractical.
In the present invention, a phase shifter network receives at an input node an input clock signal which does not contain higher order harmonics and generates first and second phase-shifted clock signals which are 90xc2x0 apart and which have the same frequency as the input clock signal. First and second voltage comparators receive the first and second phase-shifted clock signals, respectively, and generates first and second squared clock signals, respectively, which are 90xc2x0 apart and which have the same frequency as the input clock signal. A combiner combines the first and second squared clock signals to produce an output clock signal having twice the frequency of the input clock signal.